(a) Field of the Invention
The present invention relates to a fabrication method of a semiconductor device, and more particularly to a method for fabricating a thin film capacitor of a metal/insulator/metal (MIM) structure.
(b) Description of the Related Art
Recently, in a field of analog circuit requiring a high speed operation, semiconductor devices for realizing high capacitance have been developed. In general, since an upper electrode and a lower electrode of a capacitor are made of a conductive polysilicon in a case where the capacitor has a PIP structure where a polysilicon, an insulator, and a polysilicon are stacked in order, a natural oxide film is formed by an oxidation reaction at an interface between the upper and lower electrodes and a dielectric film, which results in reduction of the total capacitance.
To overcome this problem, the structure of capacitor has been changed to a metal/insulator/silicon (MIS) structure or a metal/insulator/metal (MIM) structure. Of these structures, since a capacitor of the MIM structure has a low specific resistance and no inner parasitic capacitance due to depletion, it is mainly used for high performance semiconductor devices.
Conventional techniques for a method for fabricating a thin film capacitor of the MIM structure are disclosed in U.S. Pat. Nos. 6,486,529, 6,426,250, 6,387,775, 6,313,003, and 6,284,619.
Hereinafter, a conventional method for fabricating a thin film capacitor of the MIM structure will be in brief described. FIG. 1 is a sectional view showing a thin film capacitor of a conventional MIM structure.
In order to fabricate the thin film capacitor of the MIM structure shown in FIG. 1, typical processes for fabricating a semiconductor device are first performed on a semiconductor substrate 1, a lower insulation film 2 is formed on the semiconductor substrate 1, and then a lower metal wire 3 is formed on the lower insulation film 2 and is selectively etched leaving a predetermined width.
Here, the lower metal wire 3 corresponds to a first electrode layer in the MIM capacitor.
Subsequently, an interlayer insulation film 4 is thickly deposited on an entire top surface of the lower insulation film 2 including the lower metal wire 3.
Next, a via hole 100 is formed by selectively etching the interlayer insulation film 4 and then an insulation layer 5 is formed on an inner wall of the via hole 100.
Next, metal material 6 such as tungsten is deposited on the insulation layer 5 such that the via hole 100 is completely filled. Here, the metal material 6 corresponds to a second electrode layer in the MIM capacitor.
Finally, by planarizing the metal material 6 through a chemical and mechanical polishing process and forming an upper metal wire 7 thereon, fabrication of the thin film capacitor of the MIM structure is completed.
However, in the conventional method for fabricating the MIM capacitor as described above, there is a problem of over-etch in that, when the interlayer insulation film is plasma-etched for the formation of the via hole, an etching speed is increased at an edge area (indicated by a dotted circle in FIG. 1) in the bottom of the via hole due to a plasma characteristic that charges are crowded at the edge area.
Therefore, there is a fear of leakage of current through the edge area in the over-etched bottom of the via hole, which results in malfunction of devices, even breakage of devices.